1. Field of the Invention
This invention generally relates to the field of digital electronic device testing, and particularly relates to methods and apparatuses using a scan chain to configure the operation of a built-in self-test unit.
2. Description of the Related Art
Since users generally depend upon the reliability of memory chips and other integrated circuits for their own systems to function properly, it is common practice for the chip manufacturers to test the functionality of chips at the manufacturing site before the chips are sold to users. The manufacturers"" reputations depend upon the reliability of their chips. As the line width within an integrated circuit chip continues to shrink, this reliability becomes more difficult to achieve. An ongoing challenge for the chip manufacturers is to increase the number and density of transistors on a chip without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
Before the chips are released for shipment, they typically undergo testing to verify that the circuitry for each of the major on-chip modules is functioning properly. One standard way for testing chips involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive in terms of time requirements and equipment costs.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units are now commonly incorporated into memory chips and other integrated circuits. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the chip, and to monitor a single output signal from the chip. The on-chip BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
A memory BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a memory BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the memory BIST unit is able to determine whether the memory cell is faulty. If too many errors are detected, then the fault may exist in the support circuitry for the memory cell array.
Many algorithms have been developed for detecting memory faults. The most popular algorithms are the March C algorithm and its variants such as the March C+, Smarch, or March LR algorithms. The March C algorithm may be divided into six phases. In each phase, each of the memory addresses are individually accessed.
Phase 1 of the March C algorithm writes an initial test pattern into the cells. The initial test pattern may be any desired sequence of bits, such as a xe2x80x9ccheckerboardxe2x80x9d pattern, but often simply comprises all 0""s. The initial test pattern values can be written in any order, although the cells usually are addressed consecutively from address 0 to address Nxe2x88x921 (forward) or from address Nxe2x88x921 to address 0 (backward), where N represents the number of addresses in the memory. Phases 2-5 also address each cell consecutively, executing a read operation immediately followed by a write operation at each address. Phases 2 and 3 address the memory in the forward direction from address 0 to address Nxe2x88x921, while phases 4 and 5 address the memory in the reverse direction. The first operation at each address in these phases is a read operation to verify the pattern value that was written during the previous pass. If the read operation does not return the value that was previously written, then a fault is detected. Otherwise, a write operation is performed immediately after the read operation to invert the data pattern. In phase 6, each of the cells are read to verify the pattern values written during phase 5.
Thus, BIST units are commonly included in many types of integrated circuits such as memories and operate accordingly to some predetermined algorithm to verify the functionality of the internal chip circuitry. However, electronic devices typically comprise more than the internal circuitry of a single chip. Normally they are constructed from many integrated circuit chips and many support components mounted on a circuit board.
The circuit board normally has etched conductive paths that connect the chip pins and component leads in a pattern designed to create the necessary circuits to form a complete electronic device. Solder or some other conductive adhesive couples the pins and leads to the conductive paths on the circuit board. Even if each integrated circuit and support component is verified before placement on the circuit board, there are still numerous board-level opportunities for electronic device failure. For example, the components may be damaged during the mounting procedure, breaks may occur in the conductive paths, and mechanical stress may break the adhesive coupling to the conductive paths.
As an alternative to laborious (and expensive) pin-by-pin functionality and connectivity testing, a boundary scan technique has been developed by the Joint Test Access Group (JTAG) and standardized by the Institute of Electrical and Electronic Engineers as IEEE 1149.1 xe2x80x9cIEEE Standard Test Access Port and Boundary Scan Architecturexe2x80x9d. The essence of this standard is that each integrated circuit on the circuit board will be equipped with an externally accessible boundary scan chain and standardized control circuitry. The standardized control circuitry is herein referred to as the xe2x80x9ctest access portxe2x80x9d.
The boundary scan chain consists of boundary scan cells coupled in sequence around the xe2x80x9cboundaryxe2x80x9d of the chip. Each pin of the chip is coupled via standard driver or buffer circuitry to a respective boundary scan cell, and from there to the internal logic of the chip. The boundary scan cells each include a shift register cell and a latch register cell. The shift register cell is coupled to the shift register cells of preceding and subsequent boundary scan cells. Together they form a shift register that allows information to be serially passed into and out of the boundary scan chain. The latch register cell is coupled to the shift register cell to provide its contents to the shift register cell and to subsequently receive and store the contents of the shift register cell. Together, the latch register cells form a latch register that can set the contents of the shift register and subsequently, after shifting has occurred, store and hold the contents of the shift register. The latch register cells can be further configured (for input pins) to capture the signals of their respective pins and (for output pins) to drive their contents as signals on their respective pins.
The boundary scan chain allows for external control and examination of individual pin states of the integrated circuits chips in digital electronic devices. Integrated circuit chips that comply with this standard have a set of four dedicated pins for carrying out this external control and examination. These pins are labeled Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Data can be serially shifted into the boundary scan chain via the TDI pin. Data can be serially shifted from the boundary scan chain via the TDO pin. The integrated circuit chips may be wired into a single boundary scan chain by coupling the TDO pin of one to the TDI pin of the next. The TMS and TCK pins are used to drive the standardized control circuitry that operates the boundary scan chain. All the integrated circuit chips coupled to form a single boundary scan chain can be driven in parallel by shared TMS and TCK signals. These signals and the standardized control circuitry will be described below in greater detail.
In effect, a hierarchy has developed, with the use of BIST units for testing internal circuitry and the use of boundary scan chains for testing off-chip, board-level circuitry. BIST units typically consist of hardwired circuitry that can operate at very high clock rates and that requires only a small amount of chip area. Unfortunately, hardwired circuits provide very little flexibility. When a new and unforeseen fault occurs, the BIST is of no use in locating and identifying the fault. Boundary scan chains, however, are externally accessible and generally controlled by software. Consequently when unexpected board-level faults occur, the boundary scan chain software can easily revised to locate and identify the fault, and to screen for the fault in other boards. It would be desirable to provide a BIST unit having such access and flexibility, without losing the existing advantages of high speed and small area requirements.
Accordingly, there is disclosed herein an integrated circuit device having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip, e.g. a memory. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter. The operational mode parameter may be set to allow step-by-step application of the test pattern, phase-by-phase application, or full application. In those modes where breakpoints are provided, the test access port may be used to access the boundary scan chain and register to alter the test pattern. Preferably, the boundary scan chain is also divided into portions that may be individually accessed without disturbing the bulk of the boundary scan chain, e.g. address portion, control portion, and data portion. This may advantageously lower the overhead required for customizing the test pattern. Also disclosed herein is a method for using such a configuration to verify the functionality of the application logic.